Field programmable gate arrays (FPGAs) are regular structures of logic modules communicating via an interconnect architecture of lines and switches. A user programs the logic modules and interconnect structures to perform particular functions and realize the FPGA's global function. Because of their programmability in the field, they have been widely used for rapid prototyping or reconfiguration of complex digital systems. There are many types of FPGA, such as RAM-based, EPROM switches or antifuses. Out of these, RAM-based FPGAs are the most popular and widely used.
A test procedure for a FPGA consists of successively configuring the FPGA using configuration bits and thereafter applying a test sequence using the operation inputs. The FPGA configuration corresponds to a very long sequence of bits, serially entered in the FPGA. Accordingly, the FPGA configuration process is excessively time consuming and incurs substantial reprogramming cost.
Further, the testing of an M*M matrix of programmable logic blocks (PLB) and interconnects of a RAM-based FPGA involves controlling and observing the whole matrix (Referring Paper: “Testing the interconnect of RAM-Based FPGAs” by Michel Renovell, Jean Michel Portal, Joan Figurras and Rervant Zorian in Research Journal IEEE Design and Test of Computers, March 1998). Individual access to each PLB and the interconnect lines is not possible and the FPGA does not have enough I/O pads to control and observe each PLB and interconnect line in parallel from outside. Testing for shorts and opens of interconnect lines requires two I/O pads per line, one on each line extremity. This means that, for 80 interconnect lines of a column or row, an FPGA would require 160 pads which is practically not feasible. The FPGAs usually contain four pads per column and four pads per row, i.e., for an M*M array an FPGA has 8M pads.
To reduce the required number of I/O pads one possible solution can be to perform a sort of line globalization by connecting some of the lines. For n lines, it requires 2 n pads to form only one line. Thus all vertical lines to form one snake and all horizontal lines to form another snake and the whole interconnect structure resembles a snake requiring only 4 k pads. This solution consumes a large time.
A method for interconnect and logic block testing of RAM-based FPGAs is also described in “Research Journal IEEE Design and Test Of Computers,” January-March 1998 by Renovell, Portal et. al. In this approach there are two types of inputs: operation and configuration. One operation uses inputs during normal circuit operation to apply input vectors and another usually uses configuration inputs before normal circuit operation to configure the FPGA. This approach is dependent on number/mode of configuration and still applies the test vectors from the external IO pad. Thus the earlier discussed limitations relating to IO ports still exist.